The part that slows every edge AI project down

Shipping a model is not the same as running a model.

Format conversion. Quantisation calibration. Vendor BSPs. Out-of-tree kernel modules. NPU and GPU firmware that differs across board revisions. None of this is in the paper that described your model. Nuatara handles the stack below your model — so the only thing you ship is the model.

NUATARA ENGINE Format · Quantise · Compile · Deploy NPU GPU CPU FPGA ONE API · ANY SILICON
Where the complexity lives

Your model is not the hard part.

Every layer below your ONNX file is a different problem. Nuatara owns that entire surface.

You train this
🧠
Your Model
PyTorch · TensorFlow · LiteRT / TFLite · ONNX export. The only part you control.
Gets complex here
🔀
Format Conversion
ONNX in. Per-target format out — RKNN, TensorRT, LiteRT, OpenVINO. Each needs its own export pipeline. Nuatara does this automatically from your target manifest.
TensorRTRKNNLiteRTOpenVINOONNX RT
🔢
Quantisation
INT8 calibration per model, per chip. Accuracy must be validated. Every board behaves differently.
float32→ INT8→ FP16
🧩
Silicon Targets
Declare your targets in config — Nuatara compiles and packages the right runtime artifact for each.
RK3588A311Di.MX8Jetsonx86
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BSP & Drivers
Vendor Yocto layers, out-of-tree kernel modules, NPU firmware. Each board ships a different Linux stack.
Nuatara handles this
⚡
Nuatara Engine
One inference API regardless of silicon. Add a new hardware target by updating config — no code changes, no new integration work, no rewrite.
QuantisationBSP & DriversHW Agnostic
How Nuatara works

One model. Any hardware.

Write your model once. Nuatara handles format conversion, quantisation, backend selection, and deployment.

01

Bring your model

Export from PyTorch, TensorFlow, or any framework to ONNX. That is the only step you do.

  • Standard ONNX export
  • No runtime-specific changes
  • No hardware assumptions
02

Declare your targets

List your hardware targets in a manifest file. Nuatara compiles the right runtime artifact for each — RKNN for Rockchip, TensorRT for Jetson, LiteRT for Cortex-A — and validates quantisation accuracy per chip.

  • Supported: RK3588, A311D, i.MX8, Jetson, x86
  • Auto backend: RKNN, LiteRT, TensorRT, ONNX RT
  • Precision selected per chip capability
03

One API. Any silicon.

Your application calls one inference API regardless of which chip is underneath. Add a new hardware target by updating the manifest — no code changes, no new integration work.

  • Unified inference API
  • Manifest-driven backend selection
  • Same model, every chip
Architecture

From model file to silicon — one integration.

Five layers, one codebase. Swapping the backend or adding a new silicon target is a manifest change — no rewrite.

SiliconNPU · GPU · CPU · FPGA · ASIC
Runtime Backendselected automatically from target manifest
Engine Coreload · preprocess · infer · postprocess · score
Graph Optimisation & Precisionoperator fusion · layout transform · FP32 / FP16 / INT8 per capability
Your ModelONNX · LiteRT · TorchScript — any standard export format

Deploying AI models on edge hardware?

Talk to us about your target silicon, your model, and your deployment constraints.

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